The present invention relates to a new and improved circuit arrangement for inputting control commands into a microcomputer system, wherein a microprocessor is connected to at least one read-write memory (RAM) and a read-only memory (ROM) by means of an address bus, data bus and control bus, and to a parallel input-output interface component or block by means of the address bus, an input-output bus and further lines. By means of at least one interrupt requirement input the input-output interface is connected to at least one peripheral unit.
A number of different methods have been developed for data transfer between a microcomputer system and the peripherals. Thus, for instance, with the programmed input and output of data the data transfer is controlled by a program which must be carried out by the microprocessor of the microcomputer system. Such arrangement is afflicted with the disadvantage that with an increasing number of peripheral units or peripherals there also increases the expenditure in software, and the processor, depending upon the mode of employment thereof, must scan the peripherals relatively frequently for detecting the presence of data or control commands. Thus, time is lost for performing other tasks.
With another prior art method, the so-called interrupt input, these disadvantages are partially avoided. In this case, it is common practice that, with the presence of data or control commands which are to be received an interrupt requirement or demand is transmitted to the microprocessor of the system. After accepting this interrupt requirement the microprocessor thereafter interrupts the then presently running program, intermediately stores or buffers the register contents, and by means of an interrupt program receives and processes the new data transmitted by the peripheral units or peripherals. Upon completion of the interrupt program the microprocessor continues with the main program. If there are present a number of peripheral units and there are simultaneously requested a number of interruptions, then the sequence of the data input and the processing of the data is determined by means of a priority logic.
With state-of-the-art microcomputer systems there are used interruption priority components or blocks which are simultaneously suitable for the parallel input and output of data. A component of this commercially available type, for instance TMS9901 manufactured by Texas Instruments Corp. (User's Manual TM990/100M, December 1977), possesses at its interface to the peripheral sixteen interrupt inputs and further inputs-outputs for parallely appearing data. At the interface to the microprocessor this component is provided with an interrupt output and four related address outputs and also further inputs and outputs which are required for the communication or data traffic with the microprocessor. Upon the occurrence of interrupt requirements or requests an internal priority logic determines the priority for the interrupt signals and forms the address belonging to the highest priority and also the interrupt for the microprocessor.
A disadvantage associated with the method of inputting interruptions resides in the fact that the microprocessor is forced to interrupt a running operation and to postpone the same.
With the employment of components of the type described above a running interrupt program itself can be interrupted by one or more newly occurring interrupts having a higher priority. The interleaving of interrupt programs resulting as a consequence thereof requires additional microprocessor time. A further disadvantage is manifested in the fact that there are present a relatively limited number of interrupt inputs, so that in the case of a multiplicity of control commands which are to be inputted there has to be performed an interrupt augmentation or enlargement by cascading two components or blocks. However, this requires an additional expenditure in software and, consequently, a corresponding greater amount of processor time.